fpga
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Jarvis, review this FPGA design entirely on vibes. Note: The code and README for this post is located at Vivado Review Assistant Introduction I spent the last week investigating some ways to suffer less during the peer review phase of field-programmable gate array (FPGA) development, both as the reviewer and the reviewed. And I know…
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In today’s episode of Peter Stays Relevant, we are exploring workflow automation for FPGA development. Exciting stuff, I know. More specifically, I will be demonstrating a Continuous Integration/Continuous Delivery (CI/CD) implementation targeting the Vivado development environment. I’ll also be covering all the mistakes I made as I untangle the complicated relationship between the Github Action…
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Hi, my name is Peter Simon. I’m an Electronics Engineer at NASA Glenn Research Center for the past 6 years, and I specialize in Field Programmable Gate Array (FPGA) development. I graduated with a B.S. in Computer Science from Georgia Tech in ’19 and an M.S. from Cleveland State University in ’24. I am under-qualified…
W. Peter Simon 